RISC-V VM

This project is a JS implementation of a RISC-V VM supporting the RV32I instruction set. Try it out at riscv.dfrost.net! I created the VM engine and assembler for my RISC-V bit-golf game, and decided to create a page exclusively for simulating RISC-V.

Features

The VM supports the RV32I ISA. It allows the program to be run step-by-step, until a breakpoint, or until completion. It also implements a custom ECALL, allowing the user to easily input and output values. The assembler also has many features. In addition to the base instruction set, it recognizes common pseudoinstructions, such as "li" and "j". It supports labels in jump/branch instructions and comments for more readable code. The site also displays the compiled machine code, along with the corresponding assembly, breakpoint locations, and the next line to be executed. On the right, there is a live display of the register values, along with PC and cycle count.