RISC-V CPU for Xilinx FPGA

This project implements a 6-stage pipelined CPU that runs on the PYNQ-Z1 FPGA. It is capable of executing the basic RISC-V RV32I instruction set, as well as two control status register instructions.

Memory

The memory address space is partitioned into three banks, BIOS, instruction memory, and data memory, with a fourth partition for I/O using an UART.

Performance

The processor operates at 172MHz and 1.58 cycles per instruction. It achieves such a high frequency by having a six-stage pipeline, and by avoiding complex logic for control hazards - opting to stall instead. The six stages are PC load, instruction fetch, instruction decode, arithmetic, memory access, and writeback. The data path is shown below. While designing the processor, I experimented with a wide range of architecture choices, including three-, five-, and seven-stage pipelines, branch prediction, speculative branching, out-of-order execution, and parallel execution - however this six-stage simple design yielded the best instructions per second. If I were to revisit this project, I believe that branch prediction is the most promising area to improve performance (by decreasing cycles per instruction); my efforts with it have so far been with the three-stage designs where it must take only one cycle - whereas with the deeper pipeline it can take up to three cycles. For more details the project report is included below.

Full Report